1. Field of the Invention
The present invention relates generally to preventing write fails in a memory device including a Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), and more particularly to preventing write fails that are caused by a ringing in a DQS signal applied to a DDR SDRAM during a write operation.
2. Description of the Prior Art
In general, a Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM) operates at a double speed when compared to the frequency of a clock (clk) signal, because a DDR SDRAM latches or accesses (e.g., reads and writes) data at both the rising and falling edges of a DQS signal during a write operation. In general, the controller of a DDR SDRAM provides the DQS signal (among other signals) during, for example, a write operation, and this DQS signal—at both rising and falling edges—is used to clock data into the DDR SDRAM in a write operation (and into the controller in a read operation). Consequently, a DDR SDRAM is said to operate at a double data rate.
This double data rate operation utilizing the rising and falling edges of the DQS signal is usually performed only in the input/output buffers of a DDR SDRAM. The internal operations of a DDR SDRAM, like operations of SDRAM, are performed at an interval of one clock. For example, all control signals may change only on the rising edge of the clk signal.
For the double data rate operation in a DDR SDRAM, two signals dsrt2 and dsft2 are generated based on the rising and falling edges of one pulse of the DQS signal. Data are latched at the rising edge of each of dsrt2 and dsft2 signals for the double data rate operation.
A conventional write operation of the DDR SDRAM is described with reference to FIGS. 1A–1B and 2.
Shown in FIG. 1A is a block diagram of a data input part showing the write operation of a DDR SDRAM. A DQS buffer 100 receives and buffers the DQS signal for use within the DDR SDRAM. The DQS buffer 100 outputs the signal to a DQS latch 110, which receives and latches the signal outputted by the DQS buffer 100.
A Din buffer 120 as a data input buffer receives and buffers the data DQ signal. A Din latch 130 as a data latch receives and latches the data DQ signal transferred from the Din buffer 120.
A Din IOSA 140 is an amplifier for detecting the data input/output. The Din IOSA 140 receives and amplifies the received data outputted by a Din latch 130, and then transfers the amplified data to the input/output lines gio_e, gio_o. A data input strobe pulse (dinstbp) signal as shown in FIG. 1A enables the Din IOSA 140.
Shown in FIG. 1B is a timing chart for illustrating a general write operation in a DDR SDRAM. The abbreviation “clk” is an external clock signal; “DQ” is an external input data; “algn_r” and “algn_f” are data that are latched and aligned at the falling edge of the DQS signal (i.e., a rising edge of dsft2); “dinstbp” is a signal utilized for latching the data algn_r, algn_f that are aligned in the data latch at the rising edge of dsft2 and for transferring the latched data to the global input/output bus lines; and “gio_e” and “gio_o,” respectively, are the even and odd global bus lines to which the data from the DDR SDRAM are transferred. “1st_r”, “1st_f”, “2nd_r”, and “2nd_f” (a burst length equals 4) represent the data that are inputted to the global bus lines.
Now referring to both FIGS. 1A and 1B, a DDR SDRAM write operation is described here. A “write” command (FIG. 1B) can be issued in synchronization with a clock signal (clk) applied from an external source. After a predetermined time delay, the DQS signal is applied to the DQS buffer 100 as shown in FIG. 1B. The DQS latch 110 receives the DQS signal from the DQS buffer 100 and generates dsrt2 and dsft2 signals. The dsrt2 and dsft2 are pulse signals generated in synchronization with the rising and falling edges of the DQS signal, respectively.
The data 1st_r, 1st_f, 2nd_r, and 2nd_f in the DQ signal are serially inputted to the data buffer 120 and are stored in the data latch 130 in synchronization with the rising and falling edges of the DQS signal. For example, the first data 1st_r is stored in the data latch 130 in synchronization with the rising edge of the dsrt2 signal, and a second data 1st_f is stored in the data latch 130 in synchronization with the rising edge of the dsft2 signal. The data 1st_r and 1st_f stored in the data latch 130 are then aligned in synchronization with the falling edge of the DQS signal (i.e., the rising edge of the dsft2 signal). They are then inputted to the Din IOSA 140. In FIG. 1B, the data aligned in synchronization with the falling edge of the DQS signal and are inputted to the Din IOSA 140 are represented as 1st_algn_r, 1st_algn_f, 2nd_algn_r, and 2nd_algn_f.
Next, the data 1st_algn_r, 1st_algn_f, 2nd_algn_r, and 2nd_algn_f stored in the Din IOSA 140 are transferred to the global input/output bus lines gio_e and gio_o in presence of the data input strobe pulse signal dinstbp, which enables the Din IOSA 140 operations.
As shown in FIG. 1B, the same above-mentioned operations are repeated in synchronization with the rising and falling edges of each of the second and subsequent pulses of the DQS signal.
After finishing the write operation, the DQS signal returns to a high-impedance state after the completion of a postamble.
However, now referring to FIG. 2, in a case where a ringing is present after the postamble, the 2nd_algn_r and 2nd_algn_f data, which have been stored and aligned in the Din latch 130 in synchronization with the falling edge of the last pulse of the-DQS signal (e.g., the second pulse of the DQS signal of FIG. 1), are substituted with wrong data in synchronization with the rising and falling edges of the erroneous DQS signals corrupted by the ringing. Such a malfunction caused by a ringing is shown in FIG. 2.
As described, a ringing can be generated to corrupt the DQS signal in a write operation when the DQS signal reaches a high-impedance state after completing a normal operation based on the uncorrupted DQS signal.
In general, a write failure caused by the presence of a ringing in the DQS signal in a write operation is not always generated in all motherboards. However, the write failure tends to increase as the number of memory module slots on the motherboard increases, as the clock frequency increase, and so forth as the failure may be dependent on various different development techniques utilized in developing a DDR SDRAM.
Therefore, the conventional DDR SDRAM has a problem, in that a conventional DDR SDRAM would regard the ringing present in the DQS signal as a part of the normal DQS signal and thereby would latch the wrong data at the rising and falling edges of the ringing. As a result for example and as shown in FIG. 2, the last two data 2nd_algn_r and 2nd_algn_f stored in the data latch are corrupted and the corrupted wrong data-are then transferred to the global input/output lines.